Semiconductor chip companies have on-prem Datacenters that could be present at different locations. These Datacenters primarily work in silos and are not able to use the compute and storage resources of Datacenters present in other locations or the Cloud. This is because these workloads require computation on petabytes of data, and it is inefficient to copy all this data and keep the two or more locations in sync. Due to this semiconductor and EDA industry has been slow to migrate and/or burst to the Cloud and take advantage of the latest hardware and elasticity available in the Cloud. Spillbox technology enables instant visibility to the entire dataset and low latency access to the on-prem data from the remote compute instances. This enables design and verification engineers to focus on their core needs and competency without spending time and effort for data availability.

Even within the same Datacenter or in any Cloud, data and metadata access overhead is huge for these NFS-based EDA workloads and this impacts the cost and performance. If the total time it takes to run the simulation or regression is reduced in the existing Datacenter, it can help reduce the cost for ASIC customers and/or help in a faster turnaround time. Spillbox filesystem uses a new paradigm to boost the performance and hence reduce the EDA tool cost, either within the same Datacenter or in the Cloud or remote Datacenter.

In chip verification millions of tests are run with billions of simulation cycles and compute power for running them is never enough. These millions of tests have many file systems each in terabytes and there are complex data dependencies. These workloads are metadata intensive, require high level of concurrency and require high performance storage. Spillbox technology not only extends the compute resources to the cloud and/or remote data center, but also accelerates these workloads. As design size grows, design and verification engineers have the flexibility to automatically use the latest hardware on the cloud.

The workload for backend physical design requires processing exceptionally large files, in petabytes that have extremely large memory footprint. So, any reduction in storage or speed up in processing by using latest CPUs helps in faster turnaround time (TAT) and/or reduction in cost for the ASIC customers, foundry, and EDA vendors. Also, with advanced nodes the demand for using additional compute resources is higher. Spillbox technology can accelerate the performance and seamlessly allow designers to run the same commands but use additional compute resources that are available either in the cloud or at remote datacenter(s).